Non-volatile semiconductor memory devices such as a flash EEPROM devices (hereinafter, referred to as a flash memory devices) are widely used as storage devices in portable electronic system, digital still cameras, computers, mobile communications terminals, memory cards, and the like. Flash memory devices can roughly classified as NAND flash memory devices and NOR flash memory devices. The NOR flash memory device has a cell structure whereby a plurality of memory cells are connected in parallel with a bit line. The cell structure of the NOR flash memory device is unsuitable for high-density flash memory devices since contact holes are formed on source and drain regions of each memory cell. On the other hand, the NAND flash memory device has a cell structure (or a string structure) whereby a plurality of memory cells are connected in series to a bit line. Accordingly, the NAND flash memory device enjoys a higher integration density than that of the NOR flash memory device. As well known in the art, the NAND flash memory device requires a string select transistor and a ground select transistor in respective strings. Each of the string and ground select transistors has a thin gate oxide layer of about 50 Å to 100 Å, while each of cell transistors has a gate structure where a tunnel oxide layer, a floating gate, an insulation layer and a control gate are stacked in the order stated.
FIG. 1 illustrates a block diagram of a conventional NAND flash memory device. Referring to FIG. 1, the NAND flash memory device includes a memory cell array 100, a string select line driver circuit 110, a ground select line driver circuit 120, a word line driver circuit 130, a charge pump circuit 140, a high voltage regulator circuit 150, and a block decoder circuit 160. A string corresponding to one bit line is illustrated in the memory cell array 100 of FIG. 1. A string connected to a bit line BL consists of a string select transistor SST, a plurality of memory cells (or unit cells) Cn-1 to C0 and a ground select transistor GST. The transistors SST and GST and the unit cells Cn-1 to C0 are connected to select lines SSL and GSL and word lines WLn-1 to WL0, respectively. The select lines SSL and GSL are connected to the string select line driver circuit 110 and the ground select line driver circuit 120 through corresponding transistors ST and GT, respectively. The word lines WLn-1 to WL0 are connected to the word line driver circuit 130 through corresponding select transistors WTn-1 to WT0, respectively.
The charge pump circuit 140 generates a read voltage VREAD during a read operation, and the voltage regulator circuit 150 controls the charge pump circuit 140 so that the read voltage VREAD is maintained at a constant level. The string select line driver circuit 110 receives the read voltage VREAD and drives a signal line SS with the read voltage VREAD in response to a control signal Read_EN. The ground select line driver circuit 120 receives the read voltage VREAD and drives a signal line GS with the read voltage VREAD in response to the control signal Read_EN. The word line driver circuit 130 receives the read voltage VREAD and selects one of signal lines Sn-1 to S0 in response to a word line address and the control signal Read_EN. The word line driver circuit 130 drives the selected signal line with a voltage of 0V and unselected select lines with the read voltage VREAD. The block decoder circuit 160 receives a high voltage VPP and drives a block word line BLKW in response to a block address.
As shown in FIG. 1, during a read operation, a selected word line (e.g., WL0) is driven with 0V, while unselected word lines (e.g., WLn-1 to WL1) are driven with a read voltage VREAD as a pass voltage. The pass voltage prevents unselected cells in a string from limiting an on-cell current. Like the unselected word lines, the string and ground select lines SSL and GSL are driven with the read/pass voltage VREAD in order to prevent an on-cell current from being limited. For this reason, the driver circuits 110, 120 and 130 are formed of high-voltage switches for driving corresponding signal lines with the pass voltage being a common voltage.
FIG. 2 shows a block diagram of a string/ground select line driver circuit in FIG. 1. As illustrated in FIG. 2, a string/ground select line driver circuit 110/120 consists of a high-voltage switch 112 that outputs an input voltage VREAD in response to a control signal Read_EN indicating a read operation. It is apparent to one skilled in the art that unlike conventional switches, the high-voltage switch 112 is a circuit for transferring an input voltage signal to an output voltage signal in response to a control signal.
FIG. 3 shows voltage levels of word lines WLn-1 to WL0 and select lines SSL and GSL when a control signal Read_EN is activated. As illustrated in FIG. 3, unselected word lines and select lines SSL and GSL are driven with a pass/read voltage VREAD through corresponding driver circuits, and a selected word line is driven with 0V.
The above-described NAND flash memory device has the following problem. As the NAND flash memory devices continue to become more highly integrated, and to have a larger capacity, the cell size become scaled down. Decrease in a cell size means that the thickness of the tunneling oxide layer is reduced. As described above, a gate oxide layer of respective string and ground select transistors consists of such a tunneling oxide layer. Accordingly, the gate oxide layer of the respective select transistors becomes relatively thin. Meanwhile, since a pass voltage VREAD to an unselected bit line must be sufficiently higher than the highest threshold voltage of a programmed cell, the threshold voltage distribution of programmed cells becomes relatively wide. In the case of a multi-bit flash memory device where plural threshold voltage distributions exist, the pass voltage VREAD must become higher. For example, if a thickness of a tunneling oxide layer is 6 nm and a pass voltage VREAD is 6V, an electric field of 10 MV/cm is applied across the tunneling oxide layer that is used as a gate oxide layer of the respective select transistors. The gate oxide layers can be broken down by the electric field. This causes a decrease in the reliability of the string and ground select transistors. In other words, gate oxide layers of the select transistors can become degraded owing to the high voltage that is applied during a read operation and owing to the stress of repeated read operations over time, thus causing a progressive failure. As a result, malfunction of string cells can occur.
In the case of a NAND flash memory device that uses a relatively thin oxide layer as gate oxide layers of string and ground select transistors, the electric field with respect to the gate oxide layer of the respective select transistors is larger in strength than the electric field to a tunnel oxide layer and a gate interlayer insulation layer of a cell transistor. One technique for solving this problem is to use a relatively thick oxide layer, such as the thickness adopted to high-voltage transistors, as a gate oxide layer of the string and ground select transistors. For this, the select transistors must be formed to have different threshold voltages and oxide layer thickness from the cell transistors in word lines adjacent to the select transistors. In this case, the string size is necessarily increased, and as such, it is impractical to actually adopt such a technique to the NAND flash memory device.